1. Field of the Invention
The present invention relates to a power semiconductor device and a manufacturing method thereof; more particularly, to a power semiconductor device with drain voltage protection and a manufacturing method thereof.
2. Description of the Prior Art
Due to that a power MOS (metal oxide semiconductor) transistor device has a conductivity of high voltage and high current, it tends to be damaged by an ESD pulse. In addition, in order to have a lower threshold voltage, a gate oxide layer of the power MOS transistor should be thinned in recently integrated circuits. To meet the requirement, the power MOS transistor may be easily damaged by an ESD pulse caused by friction or other reasons which are not in control. Therefore, in the application of the power MOS transistor, the power MOS transistor is necessary to be combined with an ESD protection circuit so as to prevent the power MOS transistor from being damaged. In the modern technique of manufacturing the power MOS transistor, the fabrication of the ESD protection circuit is generally performed after the fabrication of the power MOS transistor, which leads to additional manufacturing processes and costs.
FIG. 1 is a cross-sectional schematic diagram of a conventional power semiconductor device. As shown in FIG. 1, the conventional power semiconductor device 10 is formed on a semiconductor substrate 12, including a plurality of trench gate transistor devices 14 and a plurality of ESD protection devices 16. The method of forming the ESD protection devices 16 is described in the following description. A polysilicon layer 18 is formed first. Then, a P-type ion implantation process and an N-type ion implantation process are performed in sequence on the polysilicon layer 18 to form a plurality of P-type doped regions 20 and a plurality of N-type doped regions 22 in turn. The P-type doped regions 20 and the N-type doped regions 22 are alternately connected to each other, wherein any one of the P-type doped regions 20 and its adjacent N-type doped regions 22 form an ESD protection device 16 having a PN junction. The ESD protection devices 16 are connected in series between the gate and the drain of the trench gate transistor device.
However, an additional photomask to define the pattern of the polysilicon layer is required to integrate the ESD protection device into the trench gate transistor device for fabricating the power semiconductor device so that manufacturing processes are more complicated and costs are increased.